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DG308A
Data Sheet November 1999 File Number 3120.3
Quad Monolithic SPST, CMOS Analog Switch
The DG308A quad monolithic SPST, CMOS switch is latch proof and is designed to block signals up to 30VP-P when OFF. Featuring low ON resistance, low power consumption, and rail-to-rail analog signal range, this switch is ideally suited for high speed switching applications in communications, instrumentation and process control. The DG308A has single and dual supply capability. The input thresholds are CMOS compatible.
Features
* Low Power Consumption * CMOS Compatible * 15V Analog Signal Range * Single or Dual Supply Capability * Alternate Source
Functional Diagram
DG308A
Ordering Information
PART NUMBER DG308ACJ DG308ACY TEMP. RANGE (oC) 0 to 70 0 to 70 PACKAGE 16 Ld PDIP 16 Ld SOIC PKG. NO. E16.3 M16.15
IN2 IN1
S1
D1 S2
Pinout
DG308A (PDIP, SOIC) TOP VIEW
IN3
D2 S3
D3 S4
IN1 D1 S1 VGND S4 D4 IN4
1 2 3 4 5 6 7 8 -
16 IN2 15 D2 14 S2 13 V+ (SUBSTRATE) 12 NC 11 S3 10 D3 9 IN3
IN4 D4
SWITCHES SHOWN FOR LOGIC "1" INPUT
TRUTH TABLE LOGIC 0 1 Logic "0" 3.5V, Logic "1" 11V at V+ = 15V. DG308A OFF ON
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
DG308A Schematic Diagram
(One Channel)
DG308A
V+
P1
P2
P3 P4 P5 P6 P7 P8 N9 N8
S
VIN
N1 GND
N2
N3 N6 N7 N11 D N10
N4 V-
N5
2
DG308A
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V Digital Inputs, VS, VD (Note 1) . . . . . . . . . . . . . . (V-) -2V to (V+) +2V or 30mA, Whichever Comes First Continuous Current, (Any Terminal Except S) . . . . . . . . . . . . . 30mA Continuous Current, (S or D) . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . . . . 70mA
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . . 65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range "C" Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Signals on SX , DX , or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. 2. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Charge Injection, Q OFF Isolation, OIRR Source OFF Capacitance, CS(OFF) Drain OFF Capacitance, CD(OFF) Channel ON Capacitance, CD(ON) + CS(ON) DIGITAL INPUT CHARACTERISTICS Input Current with Voltage High, IIH Input Current with Voltage Low, IIL VIN = 15V, Full Temperature Range VIN = 0V, Full Temperature Range -1 0.001 -0.001 1 A A See Figure 1 See Figure 1 CL = 1F, RS = 0, VS = 0V VIN = 0V, RL = 75, VS = 2VP-P , f = 500kHz (Note 5) f = 140kHz VS = 0V VIN = 0V VD = 0V VIN = 0V VS = VD = 0V VIN = 15V 130 90 -10 78 11 8 27 200 150 ns ns pC dB pF pF pF V+ = 15V, V- = -15V, GND = 0V, TA = 25oC TEST CONDITIONS (NOTE 4) MIN (NOTE 3) TYP (NOTE 4) MAX UNITS
ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON Resistance, rDS(ON) VIN = 11V IS = -1mA, VD = +10V IS = 1mA, VD = -10V Source OFF Leakage Current, IS(OFF) VIN = 3.5V VS = 14V, VD = -14V VS = -14V, VD = 14V Drain OFF Leakage Current, ID(OFF) VS = -14V, VD = 14V VS = 14V, VD = -14V Channel ON Leakage Current, ID(ON) VIN = 11V VD = VS = 14V VD = VS = -14V -15 -5 -5 -5 60 60 0.1 -0.1 0.1 -0.1 0.1 -0.1 15 100 100 5 5 5 V nA nA nA nA nA nA
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DG308A
Electrical Specifications PARAMETER POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ Negative Supply Current, INOTES: 3. Typical values are for design aid only, not guaranteed and not subject to production testing. 4. The algebraic convention whereby the most negative value is a minimum, and the most positive is a maximum, is used in this data sheet. 5. OFF isolation = 20 Log VD /VS , where VS = input to OFF switch, and VD = output. All Channels ON or OFF VIN = 0V or 15V -100 0.001 -0.001 100 A A V+ = 15V, V- = -15V, GND = 0V, TA = 25oC (Continued) TEST CONDITIONS (NOTE 4) MIN (NOTE 3) TYP (NOTE 4) MAX UNITS
Test Circuit and Waveforms
VO = VS V+ S VS = 3V IN RL 1k CL 35pF D VO SWITCH INPUT 90% SWITCH OUTPUT 0V GND V-15V tON tOFF 90% RL RL + rDS(ON) LOGIC INPUT tr < 20ns tf < 20ns 0V 15V 50% 50% LOGIC "1" = SWITCH ON
15V
FIGURE 1. tON AND tOFF TEST CIRCUIT AND MEASUREMENT POINTS
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DG308A Die Characteristics
DIE DIMENSIONS: 2058m x 2109m METALLIZATION: Type: Al Thickness: 10kA 1kA PASSIVATION: Type: PSG Over Nitride PSG Thickness: 7kA 1.4kA Nitride Thickness:8kA 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2
Metallization Mask Layout
DG308A
PIN 14 S2 PIN 13 V+ (SUBSTRATE) PIN 11 S3
PIN 15 D2
PIN 10 D3
PIN 16 IN2
PIN 9 IN3
PIN 1 D1
PIN 8 IN4
PIN 2 IN1
PIN 7 D4
PIN 3 S1
PIN 4 V-
PIN 5 GND
PIN 6 54
5
DG308A Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280 MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
-C-
A2 B B1 C D D1 E E1 e eA eB L N
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
0.100 BSC 0.300 BSC 0.115 16 0.430 0.150
2.54 BSC 7.62 BSC 2.93 16 10.92 3.81
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DG308A Small Outline Plastic Packages (SOIC)
N INDEX AREA E -BH 0.25(0.010) M BM
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL MIN 0.0532 0.0040 0.013 0.0075 0.3859 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.3937 0.1574 MILLIMETERS MIN 1.35 0.10 0.33 0.19 9.80 3.80 MAX 1.75 0.25 0.51 0.25 10.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
1
2
3 SEATING PLANE
L
A A1
h x 45o
-A-
B C D
D -C-
A
A1 0.10(0.004) C
E e H h L
e
B 0.25(0.010) M C AM BS
0.050 BSC 0.2284 0.0099 0.016 16 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 16 0o 6.20 0.50 1.27
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
N
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